Efficiency analysis of harvester circuits

This paper summarizes findings on improving the efficiency of RF harvesting circuits. Following a Dickson charge pump model for RF-to-DC conversion, two RF harvesters were designed and are reported in this paper. The proposed topologies were designed and simulated on a 65nm RFCMOS process and optimized for operation at 953MHz and -20dBm input power, while providing reliable operation over a frequency range from 700MHz to 2.4GHz and input power levels from 0dBm to -30 dBm. While both topologies follow similar concept as the Dickson model, but differ in the way they were designed and implemented. A maximum efficiency of 78% is obtained at -20 dBm by the first proposed topology whereas an efficiency of 73% is obtained by the second topology at -15 dBm. Comparison with previous work is presented towards the end of this paper. To the best knowledge of the authors, these are the best efficiency levels to reported for an energy harvesting system under similar conditions.