Establishing a lower bound on systolic execution time

Author

Barada, H. ; El-Amawy, A.

Author_Institution

Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA

fYear

1989

fDate

26-28 Mar 1989

Firstpage

216

Lastpage

220

Abstract

A tool called the systolic precedence diagram (SPD), for use in the systematic mapping of compute-bound algorithms into time-optimal systolic architectures, is presented. The SPD graphically displays the computations in accordance with the algorithmic precedence rules under the systolic requirements. It provides a model from which parallel operations are identified and establishes a lower bound on the systolic execution time of an algorithm

Keywords

parallel algorithms; parallel architectures; algorithmic precedence rules; compute-bound algorithms; lower bound; parallel algorithms; parallel processing; systolic architectures; systolic execution time; systolic precedence diagram; Algorithm design and analysis; Communication system control; Computer architecture; Computer displays; Concurrent computing; Data mining; Flow graphs; High level languages; Systolic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

System Theory, 1989. Proceedings., Twenty-First Southeastern Symposium on

Conference_Location

Tallahassee, FL

ISSN

0094-2898

Print_ISBN

0-8186-1933-3

Type

conf

DOI

10.1109/SSST.1989.72464

Filename

72464

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2106202