DocumentCode
2106258
Title
An SFI-5 compliant 16:4 multiplexer for OC-768 systems
Author
Min Xu ; Benyamin, S. ; Xiaomin Si ; Wong, W. ; Shaeffer, D. ; Hai Tao ; Shahani, A. ; Condito, V. ; Ong, A. ; Tarsia, M.
Author_Institution
Big Bear Networks, Sunnyvale, CA, USA
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
238
Abstract
A fully integrated SFI-5 compliant 16:4 multiplexer for OC-768/STM-256 systems is implemented in a 0.18 /spl mu/m 120 GHz SiGe technology. The chip recovers sixteen 2.488 Gb/s inputs, aligns them according to the deskew channel and multiplexes them onto 4 streams of 10 Gb/s data. The measured BER is <10/sup -12/. The chip dissipates 4.8 W from 1.8 V and 3.3 V power supplies.
Keywords
BiCMOS logic circuits; Ge-Si alloys; delay lock loops; high-speed integrated circuits; multiplexing equipment; 0.18 micron; 1.8 V; 10 Gb/s data; 10 Gbit/s; 120 GHz; 120 GHz SiGe technology; 3.3 V; 4.8 W; BER; OC-768 systems; OC-768/STM-256 systems; SFI-5 compliant 16:4 multiplexer; SiGe; SiGe BiCMOS process; deskew channel; power dissipation; Calibration; Charge pumps; Circuits; Clocks; Delay lines; Jitter; Logic; Multiplexing; Phase locked loops; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234283
Filename
1234283
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