A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

Author

Uk-Rae Cho ; Tae-Hyoung Kim ; Yong-Jin Yoon ; Jong-Cheol Lee ; Dae-Gi Bae ; Nam-Seog Kim ; Kang-Young Kim ; Young-Jae Son ; Jeong-Suk Yang ; Kwon-Il Sohn ; Sung-Tae Kim ; In-Yeol Lee ; Kwang-Jin Lee ; Tae-Gyoung Kang ; Su-Chul Kim ; Kee-Sik Ahn ; Hyun-Geu

Author_Institution

Samsung Electron., Hwasung, South Korea

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

300

Abstract

A 1.2 V 72 Mb DDR3 SRAM in a 0.10 /spl mu/m CMOS process achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines reduce the power dissipation and the number of data lines by half. Clocks phase-shifted by 0/spl deg/, 90/spl deg/ and 270/spl deg/ are generated by clock adjustment circuits. On-chip input termination with linearity of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates.

Keywords

CMOS memory circuits; SRAM chips; high-speed integrated circuits; 0.10 micron; 1.2 V; 1.5 Gbit/s; 72 Mbit; CMOS process; DDR3 SRAM; clock adjustment circuits; dynamic self-resetting circuits; on-chip input termination; signal integrity; single-ended main data lines; CMOS process; Clocks; Delay; Differential amplifiers; Driver circuits; Mirrors; Power dissipation; Random access memory; Sampling methods; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234307

Filename

1234307