DocumentCode
2107266
Title
A 400MT/s 6.4GB/s multiprocessor bus interface
Author
Muljono, H. ; Beomtaek Lee ; Tian, K. ; Wang, Y.E. ; Huang, T. ; Atha, M. ; Adachi, M.
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
338
Abstract
A 0.13/spl mu/m 1.2V GTL bus interface with compensated slew rate and termination achieves 400MT/s at a 6.4GB/s data rate in a 5-load MP environment. Packaged on an FCBGA and interposer with 5:1:4 signal to power and ground ratio and routed on 12mm 45/spl Omega/ traces, the interface incorporates I/O timing self test supported by a DLL and an interpolator with 25ps peak-to-peak jitter.
Keywords
delay lock loops; jitter; multiprocessing systems; system buses; 0.13 micron; 1.2 V; 6.4 GB/s; DLL; FCBGA; GTL bus interface; I/O timing self test; compensated slew rate; interpolator; interposer; multiprocessor bus interface; peak-to-peak jitter; signal to power and ground ratio; Circuit testing; Clocks; Impedance; MOS devices; Packaging; Pins; Resistors; Test pattern generators; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234324
Filename
1234324
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