DocumentCode
2108386
Title
A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL
Author
Hsiang-Hui Chang ; Chih-Hao Sun ; Shen-Iuan Liu
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
434
Abstract
The DLL, in 0.35/spl mu/m CMOS, uses the shifted averaging VCDL to reduce the mismatch-induced timing error among the delay stages without extra hardware. The DLL can generate precise multiphase outputs with improved duty cycle, reduced skew errors, and lowered jitter. Compared with a conventional DLL, this design improves the peak-to-peak jitter by a factor of 1.4 at 150MHz.
Keywords
CMOS integrated circuits; clocks; delay lines; delay lock loops; jitter; 0.35 micron; 150 MHz; CMOS chip; clock generator; duty cycle; mismatch-induced timing error; multiphase delay-locked loop; peak-to-peak jitter; shifted averaging VCDL; skew; Accuracy; Clocks; Delay effects; Hardware; Parasitic capacitance; Power dissipation; Sun; Tail; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234373
Filename
1234373
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