A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25/spl mu/m CMOS

Author

Gu-Yeon Wei ; Stonick, J.T. ; Weinlader, D. ; Sonntag, J. ; Searles, S.

Author_Institution

Harvard Univ., Cambridge, MA, USA

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

464

Abstract

Low-jitter clock generation is a critical component for enabling robust high-speed operation of 5Gb/s backplane transceivers. The implementation of a 500MHz clock synthesizer that operates either as a multiplying phase-locked loop (MPLL) or a multiplying delay-locked loop (MDLL) is described. The choice depends on the noise characteristics of the input clock source. This MP/DLL design is implemented in a 0.25/spl mu/m CMOS process and operates with a 2.5V supply.

Keywords

CMOS digital integrated circuits; clocks; delay lock loops; digital phase locked loops; high-speed integrated circuits; integrated circuit noise; pulse generators; transceivers; 0.25 micron; 2.5 V; 5 Gbit/s; 500 MHz; CMOS; MP/DLL clock generator; backplane transceiver; input clock source; low-jitter clock generation; multiplying delay-locked loop; multiplying phase-locked loop; noise characteristics; robust high-speed operation; Backplanes; Capacitors; Clocks; Delay; Filters; Phase frequency detector; Resistors; Switches; Transceivers; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234388

Filename

1234388