Modeling of Substrate Noise Effects in Dynamic CMOS Circuits

Author

Gosavi, Sagar R. ; Al-Assadi, Waleed K. ; Burugapalli, Sasikiran

Author_Institution

Dept. of Electr. & Comput. Eng., Missouri Univ. of Sci. & Technol., Rolla, MO

fYear

2008

fDate

17-20 April 2008

Firstpage

1

Lastpage

6

Abstract

The decrease in the feature size has led to the integration of both digital and analog circuits on the same silicon die which has led to many crosstalk issues. The crosstalk due to the substrate interactions also plagiarizes complete digital systems. This paper lays emphasis on this fact and because of the vulnerability of dynamic CMOS circuits to noise; a brief study of the effects of substrate variations on the performance of the dynamic CMOS circuits is carried out in this paper. The effects of substrate noise at very high frequencies (above 10 GHz) are also depicted in this paper. In order to accurately estimate the effects of substrate noise a substrate model is proposed and verified for functionality in the last section of this paper.

Keywords

CMOS integrated circuits; analogue circuits; crosstalk; digital circuits; integrated circuit noise; analog circuit; crosstalk; digital circuit; dynamic CMOS circuit; silicon die; substrate model; substrate noise effect; Analog circuits; CMOS logic circuits; Circuit noise; Coupling circuits; Crosstalk; Digital systems; Frequency; Logic circuits; Semiconductor device modeling; Threshold voltage; Capacitive coupling; Dynamic CMOS; Monte Carlo simulation; Substrate Modeling; Substrate Noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Region 5 Conference, 2008 IEEE

Conference_Location

Kansas City, MO

Print_ISBN

978-1-4244-2076-6

Electronic_ISBN

978-1-4244-2077-3

Type

conf

DOI

10.1109/TPSD.2008.4562723

Filename

4562723