Efficient implementation of log10 lookup table in FPGA

When implementing a mathematical function in h/w, we would like to minimize the required resources. This task is critical in FPGA designs. One of the popular techniques for implementing mathematical functions in h/w, is a lookup table (LUT) based design. In order to reduce the required memory size, the common implementations use a linear or 2^nd order interpolation between a pre-defined set of input values for which the function values are stored in a LUT. In this paper we design an efficient FPGA implementation of a log10 conversion circuit. When trying to build such a circuit based on the conventional approach without scaling, one finds that the resulting error is unacceptable. We here suggest a simple ldquoautomatic scalingrdquo approach based on the mathematical properties of the log function that allows an efficient implementation. We then demonstrate the implementation of this approach in an FPGA.