Automatic synthesis of a dual-PLA controller with a counter

When datapath/controller designs are synthesized from high-level specifications, the control state graph can have hundreds of states and a large number of state transitions which depend only on the present state. For this class of finite state machines, an implementation with two PLAs and a counter can have much less area than a single-PLA implementation. This paper presents a new automatic procedure for coding the internal variables of an FSM with two PLAs and a counter in which the codes are selected to reduce the size of both PLAs. Analysis of the results shows that for a broad class of large FSMs the authors circuits have less cost than can be obtained using previously published automatic synthesis procedures