TRANS: a fast and memory-efficient path delay fault simulator

Author

Lin, Meng Chiy ; Chen, Jwu E. ; Lee, Chung Len

Author_Institution

Dept. of Electr. Eng., Chung-Hua Polytech. Inst., Hsin-Chu, Taiwan

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

508

Lastpage

512

Abstract

For path fault testing, a simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits, TRANS runs one million patterns within 2.5 hours and 2.2 mega-bytes for each circuit, except for c6288. Comparing the experimental results with those of DAC´89, TRANS achieves 85 times the gain of memory-speed product

Keywords

VLSI; circuit analysis computing; digital integrated circuits; digital simulation; fault location; logic CAD; logic testing; ISCAS benchmark circuits; TRANS; digital VLSI circuits; memory-efficient simulator; path delay fault simulator; path fault testing; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Performance gain; Propagation delay; Robustness; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326828

Filename

326828