M-testability: an approach for data-path testability evaluation

Author

Jamoussi, Mohamed ; Kaminska, Bozenn

Author_Institution

Ecole Polytech., Montreal, Que., Canada

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

449

Lastpage

455

Abstract

In this paper, a new M-testability approach is introduced. M-testability is based on a new Variable Testability Measure (VTM) appropriate in high-level synthesis. It is shown that VTM is a generalization of the C-testability concept which is extended to M-testability to deal with more general arrays such as those of non identical cells or functional primitives in data paths. The elaboration of this concept led to the development of a classified-level approach applied to the data path primitives. Some examples are given to show the practical applicability of the proposed technique in high-level synthesis

Keywords

cellular arrays; circuit CAD; design for testability; integrated circuit testing; logic CAD; logic arrays; logic testing; C-testability; M-testability; arrays; data-path testability evaluation; high-level synthesis; variable testability measure; Circuit testing; Electrical fault detection; Fabrication; High level synthesis; Large scale integration; Logic arrays; Logic circuits; Logic design; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326837

Filename

326837