Extent the retention time in DRAM using 3C decoder

The increasing mobile memory applications, such as NB, PDA, mobile phones, digital cameras, MP3 music players, and so on, bring the demands for diverse memory solutions in the post-PC era. The DRAM cells must be periodically refreshed to prevent loss of data; these refresh operations waste energy and degrade system performance. Existing DRAM devices refresh all cells at a rate determined by the leakiest cell in the device, however, most DRAM cells can retain data for significantly longer. [1] proposes a method refreshing most DRAM cells at a low rate, while selectively refreshing weak cells at a higher rate, can result in a significant decrease in refresh overhead. On the other hand, having SECDED support to cope with the soft errors in DRAM memories seems too weak. In this paper a 3C decoder with the capability of DEC/QED is proposed. This design requires no modification to DRAM. Applying on DRAM and eDRAM, this refresh controller achieves at least 75% refresh reduction, at a modest storage overhead of redundant 8KB DRAM memory. Its benefits are designing a robust DRAM system to the various applications.