Design and representation of parameterized layouts for octagonal spiral inductors

In order to reduce redesign iterations occurring in the design of analog integrated circuits, it is desirable to estimate layout-induced parasitics during the circuit synthesis phase. Since parameterized layouts allow us to build models of parasitics automatically and systematically, researchers have proposed to use them in an analog design flow so as to estimate parasitics during the circuit synthesis phase. In this paper, we propose methods for designing and representing the parameterized layout of a two-turn octagonal spiral inductor. The parameterized layout contains a parameterized 45-degree polygon. Also, the parameterized layout is process-independent and can be used to generate design-rule-correct physical layouts for given inductance values. The proposed methods are general and can be applied to the design and representation of parameterized layouts for other basic building blocks in analog integrated circuits.