Novel DSP architecture for OFDM modem systems

The paper presents application-specific instructions and DSP architecture for OFDM algorithms The proposed instructions calculate a butterfly within two cycles and reduce the computation cycles of scrambling, convolutional encoding, and timing synchronization. The proposed DSP employs a data processing unit (DPU) supporting the special instructions and an FFT address generation unit (FAGU) automatically calculating the butterfly input data addresses. The proposed DSP has been synthesized using the SEC 0.18 μm standard cell library and has a smaller area than commercial DSP chips. Performance comparisons show that the number of clock cycles improves over 10% for FFT computation and the size of the DPU decreases about 30% compared with the Camel DSP.