Low-power floating-point encoding for signal processing applications

The IEEE defined a standard for floating-point arithmetic used by processing systems (ANSI/IEEE Std 754-1985). This directive encodes floating point numbers using a maximum of 64 bits: 23 bits of fractional in single precision format and 52 bits of fractional in double precision format. The new multimedia terminals require low-power applications; the most important floating-point units (adders and multipliers) represent a significant part of total power wasted by a modern system-on-chip. They might dissipate less power by using a reduced format representation. To verify this possibility, floating-point operations are simulated by real systems using different formats. We discuss multimedia systems operating in different scenarios, such as wireless communication and image manipulation.