A novel local interconnect technology (MSD) for high-performance logic LSIs with embedded SRAM

Author

Uehara, T. ; Nakabayashi, T. ; Segawa, M. ; Yamashita, K. ; Arai, M. ; Ukeda, T. ; Yabu, T. ; Kobayashi, S. ; Yamanaka, M. ; Saiki, M. ; Okuyama, H. ; Kanda, A. ; Ogura, M.

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

1996

fDate

11-13 June 1996

Firstpage

142

Lastpage

143

Abstract

A novel local interconnect/contact technology with a self-aligned Metal-Stacked source/Drain structure (MSD) is proposed. This technology provides a self-aligned contact technology for narrow source/drain opening of 0.2 /spl mu/m width with low parasitic resistance and low junction leakage current level. Excellent cell characteristics with 6.82 /spl mu/m/sup 2/ full-CMOS SRAM have been achieved.

Keywords

CMOS logic circuits; CMOS memory circuits; SRAM chips; integrated circuit interconnections; large scale integration; MSD; embedded CMOS SRAM; junction leakage current; local interconnect technology; logic LSI; metal-stacked source/drain structure; parasitic resistance; self-aligned contact technology; Contact resistance; Leakage current; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507825

Filename

507825

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2128057