Parallel-serial concatenated coding: Design and bit error probability performance

We present a parallel-serial concatenated coding scheme with three interleavers. The scheme consists of two blocks, each composed of the cascade of an outer encoder and an inner encoder. In each part, the input words of the inner encoder are an interleaved version of the outer codewords. These two serially-concatenated codes are further concatenated in parallel, and linked by an interleaver which is inserted to shuffle the information at the input of the second block of the coding scheme. Performance of the parallel-serial concatenated block coding scheme is assessed by deriving an upper bound for the average maximum likelihood bit error probability, and illustrated through sample numerical results and comparisons.