A novel technique for the reduction of capacitance spread in high Q SC circuits

A circuit technique is proposed to reduce the capacitance spread of high-Q switched-capacitor (SC) filters, without increasing the sensitivity or requiring higher DC amplifier gain. The proposed SC integrator attenuates the input during both clock phases, so that the time constant of the integrator is realized with the product of two capacitance ratios instead of a single capacitance ratio. The capacitance spread then only increases as the square root of the time constant. The integrator is stray-insensitive. The enhancement of amplifier offset due to the proposed integrator is often negligible if the total offset of the entire SC filter is considered. A lowpass notch SC biquad is presented as an example to show the capacitance advantage of the integrator. In the numerical example, the new SC lowpass notch biquad reduces the total capacitance by a factor of more than three