Implementation of Vector Floating-point processing unit on FPGAs for high performance computing

Author

Chen, Shi ; Venkatesan, Ramachandran ; Gillard, Paul

Author_Institution

Fac. of Eng. & Appl. Sci., Memorial Univ., St. John´´s, NL

fYear

2008

fDate

4-7 May 2008

Abstract

A vector floating point unit (VFPU) for high accuracy scientific computing is reported. The core module, a vector register file, is divided into eight lanes. One lane contains 16 vector registers, each including 16times32-bit elements, and is connected to a floating point adder and a floating point multiplier. A flag register is used to indicate the calculation sequence for the specific computing model. The prototype is implemented on Xilinx Virtex II Pro, and a peak performance of 3.020 GFLOPS at 188.768 MHz has been achieved.

Keywords

field programmable gate arrays; floating point arithmetic; FPGA; Xilinx Virtex II Pro; computer speed 3.02 GFLOPS; core module; flag register; floating point adder; floating point multiplier; high accuracy scientific computing; high performance computing; vector floating-point processing unit; vector register file; CMOS technology; Computer architecture; Field programmable gate arrays; Floating-point arithmetic; High performance computing; Logic; Random access memory; Read-write memory; Registers; Signal generators; FPGA; floating point arithmetic operation; vector processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on

Conference_Location

Niagara Falls, ON

ISSN

0840-7789

Print_ISBN

978-1-4244-1642-4

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2008.4564662

Filename

4564662