Modeling of the Power Cycling Performance of a Si on Si Flip Chip Assembly

Flip chip (FC) technology offers many advantages over conventional surface mount technology, including a smaller device footprint and higher interconnection density. Low power but complex consumer items, such as mobile telecommunications devices, utilise this packaging technology and it is likely to spread to other electronics sectors where components have higher power dissipations and/or they have to operate in a hostile environment. As the scope for FC packaging broadens, a reliable means of establishing the long term performance of a particular package is necessary. Traditionally thermal cycling has been a primary reliability test for electronic assemblies including FC, however this fails to capture the behaviour of assemblies where the component thermal expansion is well matched to that of the substrate due to the isothermal heating and cooling of the assembly. In this situation power cycling offers an alternative means of determining the module performance. This paper describes the use of finite element modeling (FEM) to explore the effects of power cycling on a silicon on silicon multi-chip module (MCM) constructed with a low solder joint standoff height of 30-35 mum. Particular attention was given to the boundary conditions that are inevitably a typical of those used in traditional thermal cycling. The paper presents results of the temperature distributions throughout the assembly, which were found to depend upon the substrate base material (FR4 or copper) that the MCM was attached to. The results of the FEM analysis were verified by assembling test devices and measuring their temperature distribution under steady state and power cycling conditions. The predicted temperatures may then be used as boundary conditions in FEM of thermal stresses and fatigue in the assembly