Low-energy logic circuit techniques for multiple valued logic

Multiple valued logic (MVL) has been proposed as a means for reducing the power, improving the speed, and increasing the packing density of VLSI circuits. These performance improvements are achieved by designers who identify signal processing functions that can benefit from the design tradeoffs possible with MVL. Since advocates of MVL are accustomed to incorporating the possible tradeoffs of MVL techniques into specific VLSI design applications, these MVL designers may be able to take advantage of new energy saving circuit design techniques that may have tradeoffs that complement those of MVL. Low-energy (adiabatic) logic circuits have been proposed to reduce energy consumption of VLSI logic functions. Instead of the conventional dc power supply, these logic circuits use “ac” power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. It is possible to integrate all power switches and control circuitry on the chip with the low-energy logic. This results in better system efficiency and simpler power distribution. In this paper, concepts of adiabatic circuit design and the use of a high-frequency resonant power clock generator for adiabatic circuits will be summarized and then their possible application to low-energy, adiabatic multiple valued logic is discussed