• DocumentCode
    2140675
  • Title

    A 10-bit 60 Msps flash ADC

  • Author

    Lane, Chuck

  • Author_Institution
    Analog Devices, Greensboro, NC, USA
  • fYear
    1989
  • fDate
    18-19 Sep 1989
  • Firstpage
    44
  • Lastpage
    47
  • Abstract
    A 60-mega-sample/sec 10-bit flash analog-to-digital converter (ADC) that uses interpolation from 512 preamplifiers to derive 1023 parallel latches is described. The ADC was designed in a bipolar process offering three layers of metal interconnect and an effective emitter area of 0.8 μm2. Typical currents are 100 μA for 300-ps gate delays. Overall design concerns are discussed. The advantages of the architecture are analyzed, focusing on the interpolation technique and the comparator design
  • Keywords
    analogue-digital conversion; bipolar integrated circuits; interpolation; 10 bit; 100 muA; 300 ps; A/D convertor; architecture; bipolar process; comparator design; flash ADC; interpolation; parallel latches; preamplifiers; Analog computers; Analog-digital conversion; Capacitance; Computer architecture; Concurrent computing; Delay; Drives; Interpolation; Linearity; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Bipolar Circuits and Technology Meeting, 1989., Proceedings of the 1989
  • Conference_Location
    Minneapolis, MN
  • Type

    conf

  • DOI
    10.1109/BIPOL.1989.69457
  • Filename
    69457
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2140675