Parameterized logic power consumption models for FPGA-based arithmetic

The need for fast power estimation methods is a growing requirement in tools which perform power consumption optimization. This paper addresses the requirement by presenting a technique which is capable of providing a power estimate using only the word-level statistics of signals within an arithmetic hardware design. By abstracting away from the low-level details of a design it is possible to reduce the time required to calculate the power consumption dramatically. Power models for multiplication and addition have been constructed using an experimental method, and the operation of these models is illustrated by estimating the power consumed in logic for two example circuits: a sum of products and a parameterised polynomial evaluation. The proposed method is capable of providing an estimate within 10% of low-level power estimates given by XPower.