• DocumentCode
    2142064
  • Title

    Enabling Reconfigurable SoC in Multimedia Processing

  • Author

    Wang, Ying ; Chen, Wei-Nan ; Wang, Xiao-Wei ; You, Hong-Jun ; Peng, Cheng-Lian

  • Author_Institution
    Fudan Univ., Shanghai
  • fYear
    2007
  • fDate
    16-19 Oct. 2007
  • Firstpage
    811
  • Lastpage
    816
  • Abstract
    Multimedia processor designers are always challenged by performance, cost and flexibility. Due to the technological advance in FPGA, one of the promising solutions is to enable dynamically reconfigurable SoC in multimedia application. This paper utilizes reconfigurable SoC (RSoC) in multimedia processing. We propose a feasible run-time reconfigurable system where dynamically reconfigurable processing unit (RPU) is integrated with general purpose processor (GPP) at different abstraction level. Furthermore, a simple analysis on performance improvement is given accordingly. As a proof-of-concept, an RSoC prototype based on Xilinx Virtex-II Pro FPGA is also presented at last.
  • Keywords
    field programmable gate arrays; multimedia systems; reconfigurable architectures; system-on-chip; Xilinx Virtex-II Pro FPGA; dynamically reconfigurable processing unit; general purpose processor; multimedia processing; reconfigurable SoC; run-time reconfigurable system; Application specific integrated circuits; Costs; Digital signal processing; Field programmable gate arrays; Hardware; Information technology; Multimedia computing; Performance analysis; Prototypes; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer and Information Technology, 2007. CIT 2007. 7th IEEE International Conference on
  • Conference_Location
    Aizu-Wakamatsu, Fukushima
  • Print_ISBN
    978-0-7695-2983-7
  • Type

    conf

  • DOI
    10.1109/CIT.2007.30
  • Filename
    4385185