DocumentCode
2144344
Title
Fullwave simulation and validation of a complex packaging structure
Author
Archambeault, B. ; Connor, S. ; De Araujo, Daniel N. ; Ruehli, A. ; Schuster, C.
Author_Institution
IBM, Research Triangle Park, NC
fYear
0
fDate
0-0 0
Abstract
Most high data rate PCBs has many layers. Signals can change layers with many different configurations, and often have long stubs. All these options can have different effects on the signal, and need to be properly simulated. This paper describes the initial efforts to develop a strategy to properly analyze these complex structures by first modeling a simple via structure where a signal trace changes from one side of a reference plane to the other side of the same plane. No long via stubs are included initially. The complexity of the via structure is further increased by adding more metal layers, via stubs, and a return current via (at different distances from the signal via). Practical structures of increasing complexity are modeled such as those found in high-end servers and blade systems. The structures were simulated using a number of different simulation techniques: finite-difference time-domain (FDTD), partial element equivalent circuit (PEEC) as presented in A. E. Ruehli (1974), finite integration technique (FIT), and finite element method (FEM). It is widely accepted that if completely different simulation techniques are able to capture the proper physics of the problem and get the same results, then the simulation results are valid. Good agreement was obtained for all configurations
Keywords
circuit simulation; equivalent circuits; finite difference time-domain analysis; finite element analysis; printed circuit design; complex packaging structure; finite element method; finite integration technique; finite-difference time-domain technique; fullwave simulation; partial element equivalent circuit; signal trace changes; simulation technique; via structure; via stubs; Circuit simulation; Dielectric losses; Finite difference methods; Frequency; Harmonic analysis; Packaging; Physics; Printed circuits; Software tools; Time domain analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2006. Proceedings. 56th
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
1-4244-0152-6
Type
conf
DOI
10.1109/ECTC.2006.1645816
Filename
1645816
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