DocumentCode
2144413
Title
Error correction and parasitics de-embedding for on-wafer transistor S-parameter measurements using 4-port techniques
Author
Niu, Guofu ; Wei, Xiaoyun
Author_Institution
Electr. & Comput. Eng. Dept., Auburn Univ., Auburn, AL, USA
fYear
2008
fDate
20-23 Oct. 2008
Firstpage
472
Lastpage
475
Abstract
This paper presents the fundamentals and recent progresses of 4-port based error correction and parasitics de-embedding techniques we developed for high frequency transistor measurements. RF CMOS data from 2 to 110 GHz will be shown to illustrate various techniques.
Keywords
CMOS integrated circuits; S-parameters; calibration; error correction; integrated circuit interconnections; radiofrequency integrated circuits; transistors; 16-term model error correction; 4-port based error correction; RF CMOS data; frequency 2 GHz to 110 GHz; high frequency transistor measurements; on-wafer transistor S-parameter measurements; parasitics de-embedding techniques; single-step calibration; Calibration; Electric variables measurement; Error correction; Frequency measurement; Impedance; Microelectronics; Radio frequency; Samarium; Scattering parameters; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-2185-5
Electronic_ISBN
978-1-4244-2186-2
Type
conf
DOI
10.1109/ICSICT.2008.4734583
Filename
4734583
Link To Document