Current status and possibilities of wafer-bonding-based SOI technology in 45nm or below CMOS LSIs

Author

Yoshimi, Makoto ; Delpra, Daniel ; Cayrefourcq, Ian ; Celler, George ; Mazuré, Carlos ; Aspar, Bernard

Author_Institution

Soitec Asia, Inc., Tokyo, Japan

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

669

Lastpage

672

Abstract

The current status of SOI technology using wafer bonding is reviewed and its technological positioning in CMOS scaling is discussed. While bulk CMOS technology is encountering various kinds of critical issues, SOI technology using wafer bonding provides unique solutions by virtue of its flexible material design. Mobility enhancement through strained-SOI (sSOI) or optimization of crystal orientation (HOT, DSB), dynamic threshold voltage control by back-biasing (UT-BOX SOI), capacitor-less DRAM, etc., are promising options that can bring a breakthrough and continue proper scaling. Also, circuit layer transfer technology applied to back-side illumination of CMOS imager is presented, as a technology giving linkage with future 3D-integration of LSI system.

Keywords

CMOS image sensors; crystal orientation; large scale integration; silicon-on-insulator; wafer bonding; 3D-integration; CMOS LSI; CMOS imager; CMOS scaling; Si-SiO₂; back-side illumination; bulk CMOS technology; circuit layer transfer technology; crystal orientation; dynamic threshold voltage control; flexible material design; mobility enhancement; size 45 nm; wafer-bonding-based SOI technology; CMOS technology; Circuits; Couplings; Crystalline materials; Lighting; Random access memory; Strain control; Threshold voltage; Voltage control; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734637

Filename

4734637