DocumentCode
2146084
Title
New SRAM design using body bias technique for ultra low power applications
Author
Moradi, Farshad ; Wisland, Dag T. ; Mahmoodi, Hamid ; Berg, Yngvar ; Cao, Tuan Vu
Author_Institution
Dept. of Inf., Univ. of Oslo, Oslo, Norway
fYear
2010
fDate
22-24 March 2010
Firstpage
468
Lastpage
471
Abstract
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering supply voltage is possible. This SRAM cell is working under 0.3 V supply voltage offering a SNM improvement of 22% for the read cycle. Write Margin is not affected due to using body biasing technique. 65 nm ST models are used for simulations.
Keywords
SRAM chips; integrated circuit design; low-power electronics; SRAM design; body bias technique; standard cells; static noise margin; supply voltage; ultra low power applications; Application software; Circuit noise; Dynamic voltage scaling; Energy consumption; Low voltage; Nanoelectronics; Personal digital assistants; Portable computers; Random access memory; Threshold voltage; 65nm; Low power; SRAM; Static Noise Margin;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location
San Jose, CA
ISSN
1948-3287
Print_ISBN
978-1-4244-6454-8
Type
conf
DOI
10.1109/ISQED.2010.5450536
Filename
5450536
Link To Document