Modeling and analysis of effect on bit-line voltage caused by imprint in FeRAM

This study analyzed the effect on the bit-line voltage of imprint degradation in FeRAM. The hysteresis loop of the ferroelectric capacitor fitted by the three-line piecewise linear approximation model is proposed here to establish the relationship between bit-line voltage and imprint. Formulas are derived from this model for approximately calculation of the variation of bit-line voltage along with imprint voltage. The results show a linear dependence of the bit-line voltage on the imprint, and the scope of this linear relationship are determined by the parameters extracted from the hysteresis loop. The results also show that the ferroelectric capacitor with a more rectangular hysteresis loop shows less variation of the bit-line voltage according to imprint.