Design and performance of submicron MOSFETs on ultra-thin SOI for room temperature and cryogenic operation

The performance of a mesa-isolated CMOS technology fabricated on ultrathin (nonepitaxial) SOI (silicon on insulator) with film thickness ranging from 850 to 1800 AA is presented. Overall the data show that there is no observable reduction in surface mobility as the silicon thickness is reduced to 850 AA, indicating that the scaling of devices into the deep-submicron regime is possible. The results of a two-dimensional analytical model which accounts for the effects of silicon film thickness, buried oxide thickness, gate oxide thickness, and back-gate bias on device performance are shown. The operation of a near-intrinsic MOSFET is studied at room temperature and cryogenic temperatures. Measurements show that with the application of back-gate bias this device is suitable for low-temperature operation.<>