A multi-GHz 130ppm accuracy FLL for duty-cycled systems

Author

Wang, X. ; Busze, B. ; Romme, J. ; Vinella, R.M. ; Zhou, C. ; Philips, K. ; de Groot, H.

Author_Institution

Holst Center-IMEC, Eindhoven, Netherlands

fYear

2011

fDate

5-7 June 2011

Firstpage

1

Lastpage

4

Abstract

A frequency-locked-loop optimized for output frequency accuracy and locking time is implemented in a 90nm CMOS technology. The output frequency ranges from 7-9.8GHz with a reference frequency at 130MHz. The accuracy of the output frequency is 130ppm, achieved by minimizing and dithering the fine tuning bits of the oscillator. The estimated locking-time is below 50 reference clock cycles, thanks to the frequency locking nature. A binary frequency detector is adopted, lending the FLL naturally to a digital implementation, therefore avoiding the control voltage leakage issue. The measured phase noise @1MHz is -67dBc/Hz. The implementation offers itself a suitable solution for duty-cycled system.

Keywords

CMOS integrated circuits; frequency locked loops; oscillators; CMOS technology; binary frequency detector; duty-cycled system; frequency 1 MHz; frequency 130 MHz; frequency 7 GHz to 9.8 GHz; frequency-locked-loops; locking time; oscillator; output frequency accuracy; size 90 nm; Accuracy; Frequency locked loops; Phase noise; Steady-state; Time frequency analysis; Tuning; duty-cycle; frequency accuracy; frequency locked loop; locking time;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE

Conference_Location

Baltimore, MD

ISSN

1529-2517

Print_ISBN

978-1-4244-8293-1

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2011.5946283

Filename

5946283