Implementation of recursive and nonrecursive digital filters using the single multiplexed ROM in the quadratic residue number system

Recursive and nonrecursive digital filters have been implemented using the proposed single-multiplexed dual-clock computational module (SDCM) in the bit-slice architecture. The amount of memory requirements has been reduced to 50% required for the quadratic-residue-number system (QRNS) or modified-QRNS filter architecture. These filter architectures are suitable for single-chip VLSI implementation of complex digital filters. Though the data rate is reduced by 50%, VLSI implementation of the filter architectures using the RNS principle is certainly possible in this approach