A two-level pipeline input interface circuit with probability splitting computation function used in analog decoder

In receiver, the output of demodulator is generally ¿soft-bit¿ signal in serial form. While the channel decoder implemented by analog circuits requires parallel decoder implemented by analog circuits requires parallel computation. To decrease the complexity and power consumption of analog decoder, the paper employs 0.6 ¿m CMOS technology to design a two-level pipeline input interface circuit including two important functions: serial-to-parallel conversion and probability splitting. The interface circuit consists of four parts: sampling and holding cell, switch cell, voltage-to-current conversion cell, and probability splitting cell, which make the analog decoder avoid using ADC circuit. Simulation results show that the input interface circuit works well and reduces the chip area and power dissipation compared with that fabricated by traditional method. The maximum speed of the circuit is up to 50 MHz, and the total power consumption is 304.8 ¿W. The interface circuit can be used in implementing the analog decoders for Turbo code and LDPC code.