Compromised impedance match design for signal integrity of pogo pins structures with different signal-ground patterns

This paper proposes a systematic methodology to model the single-ended and differential pogo pin structures for the analysis of signal integrity (SI), especially the reflected noise. A measurement method is developed for de-embedding the specialized fixture in the characterization of the pogo pins. The simulation and modeling methodologies are verified by the favorable comparison with the measured results from DC to 10 GHz. Finally, an applicable range of impedance for satisfying the desired specifications of return loss is derived. By a design chart of the impedance versus the pogo pin geometry, the compromised impedance design charts for small reflection in different S/G ratios and pin patterns are given.