A novel 1.25GSPS ultra high-speed comparator in 0.18μm CMOS

Author

Han, Bao-ni ; Yang, Yin-tang ; Zhu, Zhang-ming

Author_Institution

Inst. of Microelectron., Xidian Univ., Xian, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

1957

Lastpage

1960

Abstract

Based on the preamplifier-latch theory, a new topology structure of ultra high-speed comparator with low offset voltage applied to ultra high-speed A/D converters, which is composed of a preamplifier that includes a positive and negative resistance connected in parallel as its load, a regenerative latch and a simple output stage, is proposed. The method to analyze the speed and input offset voltage of the circuit is described. Based on SMIC 0.18 μm/1.8 V mixed-signal CMOS process, the proposed comparator is designed and simulated by Cadence Spectre. Simulation results show that the circuit can work under as high a clock frequency as 1.25 GHz and its maximum offset voltage is 0.6 mV. With 1.0 V input swing, the circuit can be used to realize 10-bit resolution.

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit simulation; comparators (circuits); high-speed integrated circuits; integrated circuit design; mixed analogue-digital integrated circuits; preamplifiers; Cadence Spectre; frequency 1.25 GHz; mixed-signal CMOS process; preamplifier; preamplifier-latch theory; regenerative latch; size 0.18 μm; topology structure; ultra high-speed A/D converters; ultra high-speed comparator; voltage 0.6 mV; voltage 1.0 V; voltage 1.8 V; Bandwidth; CMOS process; Circuit simulation; Circuit topology; Clocks; Design optimization; Equations; Latches; Preamplifiers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734944

Filename

4734944