A low kick back noise latched comparator for high speed folding and interpolating ADC

This paper presents an improved latched comparator which is suitable for high speed folding and interpolation ADC. The proposed comparator minimizes the kick back noise while regenerates the analog input signals. Injection reducing switch is introduced to suppress clock feedthrough and charge injection error. Transistors in common-gate arrangement are inserted to reduce kick back noise. Simulated result of the proposed circuit in a 0.18 ¿m standard CMOS technology show that, this comparator achieves low kick back noise to 0.2 mV, exhibits low power dissipation of 53 ¿W at 1.8 V supply compared with conventional architectures at a very high speed operation of 250 MHz.