A fast-locking phase-locked loop using a seven-state phase frequency detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 ¿m 2P4 M CMOS process with a 3.3 V supply voltage. The locking time of the proposed PLL is 1.102 ¿s compared with the 2.347 ¿s of the PLL based on continuous-time PFD and the 3.298 ¿s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.