Whole-chip ESD protection scheme for CMOS mixed-mode IC´s in deep-submicron CMOS technology

Author

Ker, Ming-Dou ; Wu, Chung-Yu ; Chang, Hun-Hsien ; Wu, Tain-Shun

Author_Institution

Comput. & Commun. Res. Lab., Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

1997

fDate

5-8 May 1997

Firstpage

31

Lastpage

34

Abstract

A whole-chip ESD protection scheme with the ESD-connection diodes and a substrate-triggering field-oxide device (STFOD) are proposed to protect mixed-mode CMOS IC´s against ESD damage. The STFOD is triggered on by the substrate-triggering technique to make an area-efficient VDD-to-VSS ESD clamp circuit. The ESD-connection diodes provide the current discharging paths among the multiple separated power lines to avoid the ESD damage located at the digital-analog interface. This whole-chip ESD protection scheme has been practically verified in an L-bits DAC chip in a 0.6-μm CMOS process with a pin-to-pin ESD robustness of above 4 KV

Keywords

CMOS integrated circuits; digital-analogue conversion; electrostatic discharge; mixed analogue-digital integrated circuits; protection; 0.6 micron; 4 kV; CMOS mixed-mode IC; DAC chip; ESD-connection diode; VDD-to-VSS clamp circuit; deep-submicron technology; digital-analog interface; pin-to-pin robustness; substrate-triggering field-oxide device; whole-chip ESD protection; CMOS integrated circuits; CMOS technology; Clamps; Diodes; Electrostatic discharge; Pins; Protection; Stress; Variable structure systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606579

Filename

606579