A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers

Author

Lin, James ; Daehwa Paik ; Seungjong Lee ; Miyahara, Masaya ; Matsuzawa, Akira

Author_Institution

Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2013

fDate

22-25 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

This paper presents a 0.55 V, 7-bit, 160 MS/s pipeline ADC using dynamic amplifiers. In this ADC, dynamic amplifiers with a common-mode detection technique are used as residual amplifiers to increase its robustness against supply voltage lowering. These amplifiers also remove the unnecessary static power consumption achieving clock-scalability in power performance. The 7-bit prototype ADC fabricated in 90 nm CMOS demonstrates an ENOB of 6.0 bits at a conversion rate of 160 MS/s with an input close to the Nyquist frequency. At this conversion rate, it consumes 2.43 mW from a 0.55 V supply. The resulting FoM is 240 fJ/c.-s.

Keywords

CMOS digital integrated circuits; amplifiers; analogue-digital conversion; clocks; pipeline processing; CMOS technology; analog-to-digital converters; clock scalability; common-mode detection; dynamic amplifiers; interpolated pipeline ADC; power 2.43 mW; residual amplifiers; size 90 nm; voltage 0.55 V; Arrays; CMOS integrated circuits; Capacitors; Clocks; Interpolation; Pipelines; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2013 IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2013.6658422

Filename

6658422