DocumentCode
2156821
Title
Low ringing I/O buffer design
Author
Carro, L. ; Bego, L.J.
Author_Institution
Dept. de Engenharia Eletrica, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
Volume
2
fYear
1998
fDate
31 May-3 Jun 1998
Firstpage
57
Abstract
This paper describes the design of a new I/O buffer architecture, allowing low ringing at the presence of inductive package noise. A simple and accurate model of the I/O buffer can be used to help semi-custom users foresee PAD behavior under different load and inductive packaging situations. Analysis results and simulations of the behavioral model were validated by a discrete prototype. The new buffer design reached higher frequencies without noise degradation when compared with traditional buffer design
Keywords
buffer circuits; integrated circuit design; integrated circuit modelling; integrated circuit noise; PAD architecture; behavioral model; ground bounce; inductive package noise; low ringing I/O buffer design; semi-custom IC; Atherosclerosis; Circuits; Degradation; Frequency; Inductance; Inductors; Packaging; Parasitic capacitance; Pins; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4455-3
Type
conf
DOI
10.1109/ISCAS.1998.706840
Filename
706840
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