DocumentCode
2156911
Title
Circuit reliability simulation using TMI2
Author
Min-Chie Jeng ; Cheng Hsiao ; Ke-Wei Su ; Chung-Kai Lin
Author_Institution
Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
fYear
2013
fDate
22-25 Sept. 2013
Firstpage
1
Lastpage
7
Abstract
Using simulation to assess the impacts of various reliability mechanisms to circuit performance has become prevail for advanced technologies due to smaller headroom (=Vdd-Vth) and less design margins. This paper reviews existing circuit aging simulation approaches with focus on TMI. The limitations of aging models are also discussed so that reliability simulations can be executed more correctly with the right expectation. An example circuit under multi-waveform and multi-temperature stress is presented to illustrate reliability simulation flow through TMI.
Keywords
ageing; hot carriers; integrated circuit reliability; TMI2; circuit aging simulation; circuit performance; circuit reliability simulation; reliability mechanisms; smaller headroom; Aging; Degradation; Integrated circuit modeling; Integrated circuit reliability; SPICE; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2013 IEEE
Conference_Location
San Jose, CA
Type
conf
DOI
10.1109/CICC.2013.6658491
Filename
6658491
Link To Document