DocumentCode
2157607
Title
A 12-bit 12.5 MS/s multi-bit ΔΣ CMOS ADC
Author
Geerts, Yves ; Steyaert, Michiel ; Sansen, Willy
Author_Institution
ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
fYear
2000
fDate
2000
Firstpage
21
Lastpage
24
Abstract
The design of a third-order multi-bit ΔΣ high-speed A/D converter is described. The improved performance of multi-bit topologies is exploited to reduce the oversampling ratio to 8, while still achieving a resolution of 12-bits. A clock-speed of 100 MHz results in a 12.5 MS/s output rate. This design demonstrates the use of ΔΣ converters in an area traditionally dominated by (calibrated) pipelined A/D converters
Keywords
CMOS integrated circuits; analogue-digital conversion; delta-sigma modulation; high-speed integrated circuits; integrated circuit design; 100 MHz; 12 bit; delta-sigma converters; high-speed A/D converter; multi-bit ΔΣ CMOS ADC; oversampling ratio reduction; third-order A/D converter; Analog-digital conversion; Calibration; Circuit topology; Clocks; Costs; Energy consumption; Filters; Hardware; Modems; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5809-0
Type
conf
DOI
10.1109/CICC.2000.852610
Filename
852610
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