A 0.1–3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector

Author

Yao-Chia Liu ; Wei-Zen Chen ; Mao-Hsuan Chou ; Tsung-Hsien Tsai ; Yen-Wei Lee ; Min-Shueh Yuan

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2013

fDate

22-25 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

A 0.1-3 GHz, cell-based, fractional-N ADPLL with ΔΣ noise-shaped phase detector is presented. By dithering the reference phase and quantization phase error through an additional feedback path, linear phase detection and zero stabilization are accomplished without resort to sophisticated time to digital converter (TDC). The measured rms jitter from a 3GHz carrier is 1.9 ps with a multiplication factor of 60. Implemented in TSMC 40nm general purpose superb CMOS technology, the chip size is 280um × 240um.

Keywords

CMOS digital integrated circuits; circuit feedback; delta-sigma modulation; digital phase locked loops; phase detectors; time-digital conversion; ΔΣ noise-shaped phase detector; ADPLL; TDC; TSMC general purpose superb CMOS technology; cell-based fractional-N all digital phase-locked loop; feedback path; frequency 0.1 GHz to 3 GHz; linear phase detection; multiplication factor; quantization phase error; reference phase dithering; size 40 nm; time 1.9 ps; time to digital converter; zero stabilization; CMOS integrated circuits; Detectors; Frequency synthesizers; Monitoring; Phase frequency detector; Phase locked loops; Quantization (signal); ΔΣ phase detector; TDC; fractional-N ADPLL;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2013 IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2013.6658528

Filename

6658528