A fast-locking digital DLL with a high resolution time-to-digital converter

Author

Dandan Zhang ; Hai-Gang Yang ; Zhujia Chen ; Wei Li ; Zhihong Huang ; Lijiang Gao ; Wenrui Zhu

Author_Institution

Inst. of Electron., Beijing, China

fYear

2013

fDate

22-25 Sept. 2013

Firstpage

1

Lastpage

4

Abstract

A fast-locking digital delay-locked loop (DLL) is presented in this paper. By adopting a novel high resolution Time-to-Digital Converter (TDC), the time for generating fine-tuned codes is reduced to two clock cycles. Thus the total locking time is greatly reduced to 8 input reference clock cycles and remarkably shortened by 80% to 94.6% compared to previous closed-loop architectures. The proposed DLL has been fabricated in a 0.13μm CMOS technology and operates from 80MHz to 450MHz. The measured RMS and peak-to-peak jitters are 2.3ps and 10ps respectively.

Keywords

CMOS digital integrated circuits; delay lock loops; time-digital conversion; CMOS technology; TDC; clock cycles; closed-loop architectures; fast-locking digital DLL; fast-locking digital delay-locked loop; fine-tuned codes; frequency 80 MHz to 450 MHz; high resolution time-to-digital converter; size 0.13 mum; CMOS integrated circuits; Clocks; Delay lines; Delays; Frequency measurement; Inverters; Jitter; TDC; closed-loop DLL; fast-lock; multiphase;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2013 IEEE

Conference_Location

San Jose, CA

Type

conf

DOI

10.1109/CICC.2013.6658530

Filename

6658530