A scalable bit-sequential SIMD array for nearest-neighbor classification using the city-block metric

We present a fully scalable SIMD array architecture for a most efficient implementation of pattern classification by nearest-neighbor algorithms using the city-block metric. The elementary accumulator cell is highly optimized for a sequential accumulation of absolute integer differences, so that several hundreds of them can be easily integrated on a single chip. A two-dimensional M×N array structure, reflecting an inherent two-fold data parallelism of the applications, reduces the data transfer to off-chip memory from O(M×N) to O(M+N). Here, we discuss the realization of a VLSI structure, the system architecture, and large networks of associative blocks as possible applications