A fast pipelined FFT unit

This paper is dedicated to the presentation of the architecture of a VLSI butterfly processing element, for computing FFT in serial arithmetic. This butterfly PE uses complex samples and weights, with real and imaginary parts represented separately in full fractional two´s complement form. The PE is based on a compact serial/parallel to serial complex multiplier, which optimises complex multiplication by merging the generation and accumulation of partial products. The structure of the multiplier and the PE is presented; their performances are evaluated, including the possibility of reconfiguration, fault detection and fault tolerance