Register transfer modeling and simulation for array processors

Author

Chou, W.H. ; Kung, S.Y.

Author_Institution

Dept. of Electr. Eng., Princeton Univ., NJ, USA

fYear

1994

fDate

22-24 Aug 1994

Firstpage

111

Lastpage

122

Abstract

This paper presents a register transfer modeling scheme for array processor simulation. Its main goals are to verify the application specific design by real data computation, and to help fine tune the array architecture by precise timing analysis. The data flow graph of the design is translated into a register transfer language which is further combined with a hardware description module. An interactive simulator SISim v2.0 has been implemented to simulate the behavior of such a system. The results are compared with the expected valves to verify the array processor design. The recorded timing information can help the designer to analyze the system and improve the performance and resource utilization

Keywords

graph theory; interactive systems; parallel architectures; performance evaluation; synchronisation; virtual machines; SISim v2.0; application specific design verification; array architecture tuning; array processor design verification; array processor simulation; array processors; data flow graph; hardware description module; interactive simulator; performance; real data computation; recorded timing information; register transfer language; register transfer modeling; register transfer simulation; resource utilization; synchronization; timing analysis; Computational modeling; Computer architecture; Flow graphs; Hardware; Information analysis; Performance analysis; Process design; Registers; Timing; Valves;

fLanguage

English

Publisher

ieee

Conference_Titel

Application Specific Array Processors, 1994. Proceedings. International Conference on

Conference_Location

San Francisco, CA

ISSN

1063-6862

Print_ISBN

0-8186-6517-3

Type

conf

DOI

10.1109/ASAP.1994.331811

Filename

331811