A novel 1T1C capacitor structure for high density FRAM

Author

Jang, N.W. ; Song, Y.J. ; Kim, H.H. ; Jung, D.J. ; Koo, B.J. ; Lee, S.Y. ; Joo, S.H. ; Lee, K.M. ; Kim, K.

Author_Institution

Technol. Dev., Samsung Electron. Co., Yongin City, South Korea

fYear

2000

fDate

13-15 June 2000

Firstpage

34

Lastpage

35

Abstract

In this paper, an etching damage-free 4 Mb ferroelectric random access memory (FRAM) integration technology was for the first time developed using ferroelectric (FE) hole capacitor structure. Since the PZT capacitors are not etched, no etching damage was generated in the novel capacitor structure. The etching process issue, which is one of most critical obstacles for scaling down FRAM device, is completely resolved by using this novel FE hole structure. Therefore, the novel integration technology strongly promises to provide a reliable scaling down of FRAM device beyond 0.25 /spl mu/m technology generation.

Keywords

etching; ferroelectric capacitors; ferroelectric storage; lead compounds; random-access storage; 1T1C capacitor; 4 Mbit; PZT; PZT ferroelectric hole capacitor; PbZrO3TiO3; etching; ferroelectric random access memory; high density FRAM; integration technology; Buffer layers; Capacitors; Electrodes; Etching; Ferroelectric films; Ferroelectric materials; Metallization; Nonvolatile memory; Random access memory; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852758

Filename

852758