DocumentCode
2161522
Title
Limits of gate-oxide scaling in nano-transistors
Author
Bin Yu ; Haihong Wang ; Riccobene, C. ; Qi Xiang ; Ming-Ren Lin
Author_Institution
Adv. Micro Devices Inc., Sunnyvale, CA, USA
fYear
2000
fDate
13-15 June 2000
Firstpage
90
Lastpage
91
Abstract
This paper explores the ultimate scaling limit of gate oxide due to MOSFET gate leakage and device performance. The limit on Tox reduction with respect to gate leakage tolerance is considered by the concept of "dynamic" gate leakage in nano-scale MOSFET\´s. Tox scaling is also limited by transistor performance degradation due to the loss of inversion layer charge through gate leakage and the degradation of carrier mobility in the channel from increased scattering. All the three effects are investigated experimentally on CMOS devices with gate length down to 50 nm and gate Tox down to 12 A. The minimum Tox is proposed and the implications on voltage scaling, high-k gate dielectrics and low-temperature CMOS are discussed.
Keywords
MOSFET; carrier mobility; inversion layers; nanotechnology; MOSFET; carrier mobility; carrier scattering; dynamic gate leakage; gate oxide scaling; high-k gate dielectric; inversion layer charge; low temperature CMOS device; nano-transistor; voltage scaling; Current measurement; Degradation; Dielectrics; Gate leakage; Implants; Leakage current; MOSFET circuits; Nanoscale devices; Scattering; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-6305-1
Type
conf
DOI
10.1109/VLSIT.2000.852781
Filename
852781
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